View AD7889ACBZ-500R7_7765733.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

low voltage controller for touch screens ad7879/ad7889 rev. c information furnished by analog devices is believed to be accurate and reliable. however, no responsibility is assumed by analog devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. specifications subject to change without notice. no license is granted by implication or otherwise under any patent or patent rights of analog devices. trademarks and registered trademarks are the property of their respective owners. one technology way, p.o. box 9106, norwood, ma 02062-9106, u.s.a. tel: 781.329.4700 www.analog.com fax: 781.461.3113 ?2008C2010 analog devices, inc. all rights reserved. features 4-wire touch screen interface 1.6 v to 3.6 v operation median and averaging filter to reduce noise automatic conversion sequencer and timer user-programmable conversion parameters auxiliary analog input/battery monitor (0.5 v to 5 v) 1 optional gpio interrupt outputs ( int , penirq ) touch-pressure measurement wake-up on touch function shutdown mode: 6 a maximum 12-ball, 1.6 mm 2 mm wlcsp 16-lead, 4 mm 4 mm lfcsp applications personal digital assistants smart handheld devices touch screen monitors point-of-sale terminals medical devices cell phones functional block diagram ref+ x? y? x+ y+ filtering result registers control registers sequencer and timer ref? temperature sensor to result registers 6-to-1 mux ad7879/ ad7879-1/ ad7889/ ad7889-1 v cc / re f x+ x? y+ y? gnd aux/vbat/gpio penirq/int/dav serial port din/ add1 dout/ sda scl cs/ add0 12-bit sar adc ref? 07667-001 figure 1. general description the ad7879/ad7889 are 12-bit successive approximation analog-to-digital converters (sar adcs) with a synchronous serial interface and low on-resistance switches for driving 4-wire resistive touch screens. the ad7879/ad7889 work with a very low power supplya single 1.6 v to 3.6 v supplyand feature throughput rates of 105 ksps. the devices include a shutdown mode that reduces current consumption to less than 6 a. to reduce the effects of noise from lcds and other sources, the ad7879/ad7889 contain a preprocessing block. the prepro- cessing function consists of a median filter and an averaging filter. the combination of these two filters provides a more robust solution, discarding the spurious noise in the signal and keeping only the data of interest. the size of both filters is programmable. other user-programmable conversion controls include variable acquisition time and first conversion delay; up to 16 averages can be taken per conversion. the ad7879/ad7889 can run in slave mode or standalone (master) mode, using an automatic conversion sequencer and timer. the ad7879/ad7889 have a programmable pin that can operate as an auxiliary input to the adc, as a battery monitor, or as a gpio. in addition, a programmable interrupt output can operate in three modes: as a general-purpose interrupt to signal when new data is available ( dav ), as an interrupt to indicate when limits are exceeded ( int ), or as a pen-down interrupt when the screen is touched ( penirq ). the ad7879/ad7889 offer temp- erature measurement and touch-pressure measurement. the ad7879 is available in a 12-ball, 1.6 mm 2 mm wlcsp and in a 16-lead, 4 mm 4 mm lfcsp. the ad7889 is available in a backside-coated version of the wlcsp. both parts support an spi interface (ad7879/ad7889) or an i 2 c interface (ad7879-1/ad7889-1).
ad7879/ad7889 rev. c | page 2 of 40 table of contents features .............................................................................................. 1 applications ....................................................................................... 1 functional bloc k diagram .............................................................. 1 general description ......................................................................... 1 revision history ............................................................................... 2 specificati ons ..................................................................................... 3 spi timing specifications (ad7879/ad7889) ......................... 4 i 2 c timing specifications (ad7879 - 1/ad7889 -1).................. 5 absolute maximum ratings ............................................................ 6 thermal resistance ...................................................................... 6 esd caution .................................................................................. 6 pin configurations and function descriptions ........................... 7 typical performance characteristics ............................................. 9 terminology .................................................................................... 12 theory of operation ...................................................................... 13 touch screen principles ............................................................ 13 measuring touch screen inputs ............................................... 14 touch - pressure measurement .................................................. 15 temperature measurement ....................................................... 15 median and averaging filters ....................................................... 17 aux/vbat/gpio pin ................................................................... 18 auxiliary input ........................................................................... 18 battery input ............................................................................... 18 limit comparison ...................................................................... 18 gpio ............................................................................................ 18 conversion timing ........................................................................ 20 register map ................................................................................... 21 detailed register descriptions ..................................................... 22 control registers ............................................................................ 26 control register 1 ...................................................................... 26 control register 2 ...................................................................... 28 control register 3 ...................................................................... 29 interrupts ..................................................................................... 30 synchronizing the ad7879/ad7889 to the host cpu ........ 31 serial interface ................................................................................ 32 spi interface ................................................................................ 32 i 2 c- compatible interface .......................................................... 34 grounding and layout .................................................................. 37 lead frame chip scale packages ............................................. 37 wlcsp assembly considerations ........................................... 37 outline dimensions ....................................................................... 38 ordering guide .......................................................................... 39 revision history 11 /10 r ev. b to rev. c ch anges to table 2 ............................................................................ 3 added conversion timing s ection .............................................. 20 add ed figure 34 .............................................................................. 29 1/10 rev. a to rev. b updated outline dimensions ....................................................... 37 changes to ordering guide .......................................................... 38 3/09 rev. 0 to rev. a added ad7889 and backside - coated wlcsp ......... throughout change to battery monitor, input voltag e range parameter ..... 3 changes to table 4 ............................................................................ 6 added thermal resistance section and table 5; renumbered sequentially ................................................................ 6 changes to pin configurations and function descriptions section ................................................................................................ 7 added table 7 .................................................................................... 8 changes to first method section ................................................. 15 changes to median and ave raging filters section .................... 17 changes to gpio interrupt enable (bit 12, control register 3, address 0x03) section ................................................................... 19 changes to table 13 ....................................................................... 22 changes to adc channel (control register 1, bits[14:12]) section .............................................................................................. 26 changes to power management (control register 2, bits[15:14]) section ........................................................................ 27 changes to dav data available interrupt section ................. 29 changes to int out - of - limit interrupt section .................... 29 changes to writing data section ................................................. 31 changes to reading data section and figure 40 ....................... 32 changes to f igure 41 ...................................................................... 33 changes to writing data over the i 2 c bus section .................... 34 changes to figure 44 ...................................................................... 35 updated outline dimensions ....................................................... 37 changes to ordering guide. ......................................................... 38 10/08 revision 0: initial version
ad7 879/ad7889 rev. c | page 3 of 40 specifications v cc = 1.6 v to 3.6 v, t a = ?40c to +85c, unless otherwise noted. table 1. parameter min typ max unit test conditions/comments dc accuracy resolution 12 bits no missing codes 11 12 bits integral nonlinearity (inl) 1 3 lsb lsb size = 390 v. differential nonlinearity (dnl) 1 lsb size = 390 v . negative dnl ?0.99 lsb positive dnl 2 lsb offset error 1, 2 2 6 lsb gain error 1, 2 4 lsb noise 3 70 v rms power supply rejection 3 60 db internal clock frequency 2 mhz internal clock accuracy 1.8 2.2 mhz switch drivers on resistance 1 y+, x+ 6 ? y ?, x? 5 ? analog inputs inp ut voltage range 0 v cc v dc leakage current 0.1 a input capacitance 30 pf accuracy 0.3 % temperature m easurement temperature range ?40 +85 c resolution 0.3 c accuracy 2 2 c calibrated at 25c . battery monitor input voltage range 0.5 5 v input impedance 3 16 k? accuracy 2 5 % uncalibrated accuracy . logic inputs (din, scl, cs , sda, gpio) input high voltage, v inh 0.7 v cc v input low voltage, v inl 0.3 v cc v input current, i in 0.01 a v in = 0 v or v cc . input capacitance, c in 3 10 pf logic outputs (dout, gpio, scl, sda, int ) output high voltage, v oh v cc ? 0.2 v output low voltage, v ol 0.4 v floating - state leakage current 0.1 a floating - state output capacitance 2 5 pf conversion rate 3 conversion time 9.5 s including 2 s of acquisition time , mav filter off . 2 s of additional tim e is required if mav filter is on. throughput rate 105 ksps
ad7879/ad7889 rev. c | page 4 of 40 parameter min typ max unit test conditions/comments power requirements v cc 1.6 2.6 3.6 v specified performance . i cc digital inputs = 0 v or v cc . converting mode 480 650 a adc on, pm = 10 . static 406 a adc and temperature sensor are off; the reference and oscillator are on; pm = 01 or 11. shutdown mode 0.5 6 a pm = 00 . 1 see the terminology section. 2 guaranteed by characterization; not production tested. 3 sample tested at 25c to ensure compliance. spi timing specifica tions (ad7879 / ad78 8 9) v cc = 1.6 v to 3.6 v, t a = ?40c to +85c , unless otherwise noted. sample tested at 25c to ensure compliance. all input signals are sp e cified with t r = t f = 5 ns (10% to 90% of v cc ) and timed from a voltage level of 1.4 v. table 2. parameter 1 limi t unit description f scl 5 mhz m ax t 1 5 ns min cs falling edge to first scl falling edge t 2 20 ns min scl high pulse width t 3 20 ns min scl low pulse width t 4 15 ns min din setup time t 5 15 ns min din hold time t 6 20 ns max dout access time after scl falling edge t 7 16 ns max cs rising edge to dout high impedance t 8 15 ns min scl rising edge to cs high 1 guaranteed by design; not production tested. cs scl din dout t 1 1 16 15 msb lsb 2 3 msb lsb 1 2 15 16 t 2 t 4 t 5 t 3 t 6 t 7 t 8 07667-002 figure 2 . detailed spi timing diagram
ad7 879/ad7889 rev. c | page 5 of 40 i 2 c timing specificati ons (ad7879 -1/ ad78 89-1) v cc = 1.6 v to 3.6 v, t a = ?40 c to +85c, unless otherwise noted. sample tested at 25c to ensure compliance. all input signals are timed from a voltage level of 1.4 v. table 3. parameter 1 limit unit description f scl 400 khz m ax t 1 0.6 s min start condition hold time, t hd; sta t 2 1.3 s min clock low period, t low t 3 0.6 s min clock high period, t high t 4 100 ns min data setup time, t su; dat t 5 300 ns min data hold time, t hd; dat t 6 0.6 s min stop condition setup time, t su; sto t 7 0.6 s min start condition setup time, t su; sta t 8 1.3 s min bus - free time between stop and start conditions, t buf t r 300 ns max clock/data rise time t f 300 ns m ax clock/data fall time 1 guaranteed by design; not production tested. 07667-003 scl sda t r t f t 2 t 5 t 1 t 3 t 4 stop st art stop st art t 7 t 6 t 1 t 8 figure 3 . detailed i 2 c timing diagram
ad7879/ad7889 rev. c | page 6 of 40 absolute maximum rat ings t a = 25c , unless otherwise noted . table 4. parameter rating v cc to gnd ?0.3 v to +3.6 v analog input voltage to gnd ?0.3 v to v cc + 0.3 v aux/vbat to gnd ?0.3 v to + 5 v digital input voltage to gnd ?0.3 v to v cc + 0.3 v digital output voltage to gnd ?0.3 v to v cc + 0.3 v input current to any pin except supplies 1 10 ma esd rating (x+, y+, x ?, y?) air discharge h uman b ody m odel 15 kv contact h uman b ody m odel 10 kv esd rating ( all other pins) human body discharge 4 kv field - induced charge d device model 1 kv machine model 0.2 kv operating temperature range ?40c to +85c storage temperature range ?65c to +150c junction temperature 150c power dissipation wlcsp (4 - layer board) 866 mw lfcsp (4 - layer board) 2.138 w ir reflow peak temperature 260c (0.5c) lead temperature (soldering 10 sec) 300c 1 transient currents of up to 100 ma do not cause scr latch - up. stresses above those listed under absolute maximum ratings may cause permanent damage to the device. this is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational se ction of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. thermal resistance ja is specified for the worst - case conditions, that is, a device soldered in a circuit board for surface - mount packages. table 5 . thermal resistance package type 1 ja unit 12- ball wlcsp 75 c/w 16- lead lfcsp 30.4 c/w 1 4- layer board. 200 a i ol 200 a i oh 1.4v t o output pin c l 50pf 07667-004 figure 4 . circuit used for digital timing esd caution
ad7 879/ad7889 rev. c | page 7 of 40 pin configuration s and function descrip tions 07667-005 top view (bal l side down) not to scale aux/ vb a t/ gpio v cc /ref x+ y+ dout din x? sc l gnd y? 1 a b c d 2 3 bal l a1 indic at or penirq/ int/d av cs figure 5. ad7879 /ad7889 wlcsp pin configuration 07667-006 top view (bal l side down) not to scale aux/ vb a t/ gpio v cc /ref x+ y+ sd a add1 x? sc l gnd y? 1 a b c d 2 3 bal l a1 indic at or penirq/ int/d av add0 figure 6. ad7879 -1/ad7889- 1 wlcsp pin configuration table 6 . pin funct ion descriptions , wlcsp ball no. mnemonic description ad7879/ ad7889 ad7879 - 1/ ad7889 -1 1a 1a aux/vbat/gpio this p in can be programmed as an auxiliary input to the adc (aux) , as a battery measur e- ment input to the adc ( vbat ) , or as a general - purpose dig ital input/output (gpio) . 1b 1b penirq / int / dav interrupt output. this pin is asserted when the screen is touched ( penirq ), when a measure - ment exceeds the preprogrammed limits ( int ), or when new data is available in the registers ( dav ) . active low, internal 50 k ? pull - up resistor. 1c n/a dout spi serial data output for the ad7879/ad7889. n/a 1c sda i 2 c serial data input and output for the ad7879 -1/ad7889-1. 1d 1d scl serial interface clock input. 2a 2a v cc /ref power supply input and adc reference . 2b n/a cs chip select for the spi serial interface on the ad7879/ad7889. active low. n/a 2b add0 i 2 c address bit 0 for the ad7879 -1/ad7889- 1. this pin can be tied high or low to determine an address for the ad7879 -1/ad7889-1 (see table 25 ). 2c n/a din spi serial data input to the ad7879/ad7889. n/a 2c add1 i 2 c address bit 1 for the ad7879 -1/ad7889- 1. this pin can be tied high or low to determine an address for the ad7879 -1/ad7889-1 (see table 25 ). 2d 2d gnd ground. ground reference point for all circuitry on the ad7879/ad7889. all analog input signals and any e x ternal reference signal should be referred to this voltage. 3a 3a x+ touch screen input channel. 3b 3b y+ touch screen in put channel. 3c 3c x? touch screen input channel. 3d 3d y? touch screen input channel.
ad7879/ad7889 rev. c | page 8 of 40 07667-007 pin 1 indic at or 1y+ 2 nc 3 nc 4x? 11 nc 12 10 nc 9 dout 5 y? 6 din 7 gnd 8 scl 15 v cc /ref 16 x+ 14 13 aux/vb a t/gpio ad7879 top view (not to scale) penirq/int/d av cs notes 1. nc = no connect 2. the exposed p ad is not connected internal ly. for increased reliabilit y of the solder joints and maximum therma l ca p abilit y , it is recommended th a t th e p ad be soldered t o the ground plane. figure 7 . ad7879 lfcsp pin configuration 07667-008 pin 1 indic at or 1y+ 2 nc 3 nc 4x? 11 nc 12 10 nc 9 sda 5 y? 6 add1 7 gnd 8 scl 15 v cc /ref 16 x+ 14 13 aux/vb a t/gpio ad7879-1 top view (not to scale) penirq/int/d av add0 notes 1. nc = no connect 2. the exposed p ad is not connected internal ly. for increased reliabilit y of the solder joints and maximum therma l ca p abilit y , it is recommended th a t the p ad be soldered t o the ground plane. figure 8. ad7879 - 1 lfcsp pin configuration table 7 . pin function descriptions , lfcsp pin no. mnemonic description ad7879 ad7879 -1 1 1 y+ touch screen input channel. 2, 3, 10, 11 2, 3, 10, 11 nc no connect. 4 4 x? touch screen input channel. 5 5 y? touch screen input channel. 6 n/a din spi serial data inp u t to the ad7879. n/a 6 add1 i 2 c address bit 1 for the ad7879 -1 . this pin can be tied high or low to determine an address for the ad7879 -1 (see table 25 ). 7 7 gnd ground. ground reference point for all circuitry on the ad7879 . al l analog input signals and any e x ternal reference signal should be referred to this voltage. 8 8 scl serial interface clock input. 9 n/a dout spi se rial data output for the ad7879 . n/a 9 sda i 2 c serial data input and output for the ad7879 -1. 12 12 penirq / int / dav interrupt output. this pin is asserted when the screen is touched ( penirq ), when a measure - ment exceeds the preprogrammed limits ( int ), or when new data is available in the registers ( dav ). active low, internal 50 k ? pull - up resistor. 13 13 aux/vbat/gpio this p in can be programmed as an auxiliary input to the adc (aux) , as a battery measur e- ment input to the adc ( vbat ) , or as a general - purpose digital input/output (gpio) . 14 n/a cs chip select for the spi serial interface on the ad7879. active low. n/a 14 add0 i 2 c address bit 0 for the ad7879 -1 . this pin can be tied high or low to determine an address for the ad7879 - 1 (see table 25). 15 15 v cc /ref power supply input and adc reference. 16 16 x+ touch screen input channel. ep exposed pad. the exposed pad is not connected internally. for increased reliability of the solder joints and maximum thermal capability, it is recommended that the pad be soldered to the ground pl ane.
ad7 879/ad7889 rev. c | page 9 of 40 typical performance characteristics t a = 25c, v cc = 2.6 v, f s cl = 2 mhz, unless otherwise noted. 475 470 465 460 455 450 445 440 435 430 425 ?40 ?25 ?10 10 25 40 55 70 85 temperature (c) current (a) 07667-009 figure 9 . supply current vs. temperature 700 600 500 400 300 200 100 0 1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6 v cc (v) current (a) 07667-010 figure 10 . supply current vs. v cc 4.0 3.5 3.0 2.5 2.0 1.5 1.0 0.5 0 ?40 ?25 ?10 10 25 50 75 100 temperature (c) current (a) 07667-012 figure 11 . full power - down i dd vs. temperature 1.0 ?1.0 ?0.8 ?0.6 ?0.4 ?0.2 0 0.2 0.4 0.6 0.8 temperature (c) gain error variation (lsb) 07667-011 2.6v 3.6v 1.6v 85 ?40 ?25 ?10 10 25 40 55 70 figure 12 . change in adc gain vs. temperature 07667-013 1.0 ?1.0 ?0.8 ?0.6 ?0.4 ?0.2 0 0.2 0.4 0.6 0.8 temperature (c) offset variation (lsb) 2.6v 3.6v 1.6v 85 ?40 ?25 ?10 10 25 40 55 70 figure 13 . change in adc offset vs. temperature 2.0 ?2.0 ?1.5 ?1.0 ?0.5 0 0.5 1.0 1.5 0 4096 3584 3072 2560 2048 1536 1024 512 code inl (lsb) 07667-014 figure 14 . adc i nl
ad7879/ad7889 rev. c | page 10 of 40 1.0 0.8 0.6 0.4 0.2 0 ?0.2 ?0.4 ?0.6 ?0.8 ?1.0 1 501 1001 1501 2001 2501 3001 3501 4001 code dnl (lsb) 07667-015 figure 15 . adc dnl 7 6 5 4 3 2 1 0 1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6 v cc (v) r on (?) 07667-016 x+ t o v cc y+ t o v cc x? t o gnd y? t o gnd figure 16 . switch on resistance vs. v cc (x+, y+: pin to v cc ; x ?, y?: pin to gnd) 6.0 5.5 5.0 4.5 4.0 3.5 3.0 ?40 ?25 ?10 10 25 40 55 70 85 temperature (c) r on (?) 07667-017 x+ t o v cc y+ t o v cc x? t o gnd y? t o gnd figure 17 . switch on resistance vs. temperature (x+, y+: pin to v cc ; x ?, y?: pin to gnd) 2370 2369 2368 2367 2366 2365 2364 2363 2362 2361 2360 ?40 ?25 ?15 ?5 5 15 25 35 45 55 65 temperature (c) adc code (decimal) 07667-018 75 85 figure 18 . adc code vs. temperature (fixed analog input)
ad7 879/ad7889 rev. c | page 11 of 40 1400 1200 1000 800 600 400 200 0 2.2 2.3 2.4 2.5 2.6 2.7 2.8 2.9 3.0 3.1 3.2 3.3 3.4 3.5 3.6 v cc (v) temperature (code) 07667-019 figure 19 . temperature code vs. v cc for 25c 0 ?20 ?40 ?60 ?80 ?100 ?120 ?140 ?160 0 1603 3206 4809 6412 8015 9618 11221 12824 14427 16030 17633 19236 20839 22442 24045 25648 27251 28854 30457 32060 33663 35266 36869 frequency (hz) input tone amplitude (db) 07667-020 snr = 61.58db thd = 72.34db figure 20 . typical fft plot for the auxiliary channels at 25 khz sampling rate and 1 khz input frequency 250 200 150 100 50 0 number of units ?4 ?3 ?2 ?1 0 error (%) mean: ?1.98893 sd: 0.475534 07667-021 figure 21 . typical uncalibrated accuracy for the battery channel (25c)
ad7879/ad7889 rev. c | page 12 of 40 terminology differential nonlinearity (dnl) dnl is the difference betwe en the measured an d the ideal 1 lsb change between any two adjacent codes in the adc. integral nonlinearity (inl) inl is the maximum deviation from a straight line passing through the endpoints of the adc transfer function. the endpoints of the transfer function are zero scale at 1 lsb below the first code transition and full scale at 1 lsb above the last code transition. gain error gain error is the deviation of the last code transition (111 110 to 111 111) from the ideal (v ref ? 1 lsb) after the offset error has been calibrated out. offset error offset error is the deviation of the first code transition (00 000 to 00 001) from the ideal (agnd + 1 lsb). on resistance on resistance is a measure of the ohmic resistance between the drain and the source of the switch d rivers .
ad7 879/ad7889 rev. c | page 13 of 40 theory of operation the ad7879/ad7889 are a complete 12 - bit data acquisition system for digitizing positional inputs from a 4 - wire resistive touch screen. to support this function, data acquisition on the ad7879/ad7889 is highly programmable to ensure accurate and noise - free results from the touch screen. the core of the ad7879/ad7889 is a high speed, low power, 12- bit analog - to - digital converter (adc) with an input multi - plexer, on - chip track - and - hold, and on - chip clock. conversion results are s tored in on - chip result registers . the results from the auxiliary input or the battery input can be compared with high and low limits stored in limit registers to generate an out - of - limit interrupt ( int ). the ad7879/ad7889 also conta in low resistance analog switches to switch the x and y excitation voltages to the touch screen and to the on - chip temperature sensor. the high speed spi serial bus provides control of the devices, as well as com - munication with the devices. the ad7879 - 1/a d7889 - 1 are available with an i 2 c interface. operating from a single supply from 1.6 v to 3.6 v, the ad7879/ ad7889 offer a throughput rate of 105 khz. the device is avail - able in a 1.6 mm 2 mm , 12 - ball wafer level chip scale package (wlcsp) and in a 4 m m 4 mm , 16- lead lead frame chip scale package (lfcsp). the ad7879/ad7889 have an on - chip sequencer that schedules a sequence of preprogrammed conversions. the conversion sequence starts automatically when the screen is touched or at preset intervals, us ing the on - board timer. to ensure that the ad7879 /ad7889 work well with different touch screens, the user can select the acquisition time. a programmable delay ensure s that the voltage on the touch screen settle s before a measurement is taken. to he lp re du ce noise in the system, the adc takes up to 16 conversion results from each channel and writes the average of the results to the register. to further improve the performance of the ad7879/ad7889, the median filter can also be used if there is noise present in the system. touch screen princip les a 4 - wire touch screen consists of two flexible, transparent, re sistive - coated layers that are normally separated by a small air gap (see figure 22) . the x layer has conductive electrodes r unning down the left and right edges, allowing the application of an excitation voltage across the x layer from left to right. 07667-022 x+ x? y? y+ conductive electrode on bot t om side plastic film with trans p aren t , resistive co a ting on bot t om side plastic film with trans p aren t , resistive co a ting on top side lcd screen conductive electrode on to p side figure 22 . basic construction of a touch screen the y layer has conductive electrodes running along th e top and bottom edges, allowing the application of an excitation voltage down the y layer from top to bottom. provided that the layers are of uniform resistivity, the voltage at any point between the two electrodes is proportional to the horizontal posit ion for the x layer and the vertical position for the y layer. when the screen is touched, the two layers make contact. if only the x layer is excited, the voltage at the point of contact and , therefore , the horizontal position, can be sensed at one of the y layer electrodes. similarly, if only the y layer is excited, the voltage and , therefore , the vertical position, can be sensed at one of the x layer electrodes. by switching alternately be tween x and y excitation and measuring the voltages, the x and y coordinates of the contact point can be determined . in addition to measuring the x and y coordinates, it is also possible to estimate the touch pressure by measuring the co n tact resistance between the x and y layers. the ad7879 / ad7889 are designed to fac ilitate this measurement.
ad7879/ad7889 rev. c | page 14 of 40 figure 23 shows an equivalent circuit of the analog input stru c ture of the ad7879/ad7889, showing the touch screen switches, the mai n analog multiplexer, the adc, and the dual 3 - to - 1 multi - p lexer that selects the reference source for the adc. aux/vbat/gpio 12-bit successive approximation adc with track-and-hold input mux temperature sensor y? y+ x? x+ v cc ref? in+ ref+ dual 3-to-1 mux x? y? gnd x+ y+ v cc 07667-023 figure 23 . analog input structure the ad7879 /ad7889 can be set up to automatically convert either sp e cific input channels or a sequence of channels. the results of the adc conversions are stored in the result register s. when measuring the ancillary analog inputs (aux, temp, or vbat), the adc uses a v cc reference and the measurement is referred to gnd. measuring touch scre en inputs when measuring the touch screen inputs, it is possible to us e v cc as a reference or instead to use the touch screen excit a tion voltage as the reference and to perform a ratiometric, diff e rential measurement. the differential method is the default method and is selected by clearing the ser/ dfr bit (bit 9 in control register 2) to 0. the single - ended method is selected by setting this bit to 1. single - ended method figure 24 illustrates the single - ended method for the y position. for the x position, the excitation voltag e is applied to x+ and x ? and the voltage is measured at y+. adc ref+ input (via mux) x+ ref? touch screen y+ y? gnd v ref v cc 07667-024 figure 24 . single - ended conversion of touch screen inputs the voltage seen at the input to the adc in figure 24 is ytotal y cc in r r vv ? = (1 ) the advantage of the single - ended method is that the touch screen excitation voltage is switched off when the signal is acquired. because a screen can draw over 1 ma, this is a signif i cant consideration for a battery - powered system. the disadvantage of t he single - ended method is that voltage drops across the switches can introduce errors. touch screens can have a total end - to - end resi stance ranging from 200 ? to 900 ?. by taking the lowest screen resistance of 200 ? and a typical switch resistance of 14 ?, the user can reduce the apparent excitation voltage to 200/228 100 = 87% of its actual value. in addition, the voltage drop acros s the low - side switch adds to the adc input voltage. this introduces an offset into the input voltage ; thus, it can ne v er reach 0. ratiometric method the ratiometric method illustrated in figure 25 shows the negative input of the adc reference connected to y ? and the positive input connected to y+. thus, the screen excitation voltage provides the reference for the adc. the input of the adc is connected to x+ to determine the y position. adc ref+ input (via mux) ref? v cc x+ touch screen y+ y? gnd 07667-025 figure 25 . ratiometric conversion of touch screen inputs for greater accuracy, the ratiometric method has two significant advantages. one is that t he reference to the adc is provided from the actual voltage across the screen; therefore, any voltage dropped across the switches has no effect. the other advantage is that b ecause the measurement is ratiometric, it does not matter if the voltage across the screen varies in the long term. ho w ever, it must not change after the signal has been acquired. the disadvantage of the ratiometric method is that th e screen must be powered up at all times because it provides the reference voltage for the adc.
ad7 879/ad7889 rev. c | page 15 of 40 touch - pressure measurement the pressure applied to the touch screen by a pen or finger can also be measured with the ad7879/ad7889 using some simple calculatio ns. the contact resistance between the x and y plates is measured , providing a good indication of the size of the depressed area and, therefore, the applied pressure. the area of the spot that is touched is proportional to the size of the object touching i t. the size of this resistance (r touch ) can be calculated using two di f ferent methods. first method the first method requires the user to know the total resistance of the x - plate tablet (r x ). three touch screen conversions are required: m easurement of the x position, x position (y+ input); measurement of the x+ input with the excitation voltage applied to y+ and x ? (z1 measurement); and m easurement of the y ? input with the excitation voltage applie d to y+ and x ? (z2 measurement). these three measurements are illustrated in figure 26 . the ad7879 /ad7889 h ave two special adc channel sett ings that configure the x and y switches for the z1 and z2 measure - ments and store the results in the z1 and z2 result register s. the z1 measurement is selected by setting the chnl add[2:0] bits to 101 in control register 1 (address 0x01); the result is st ored in the x+ (z1) result register (address 0x0a). the z2 measurement is selected by setting the chnl add[2:0] bits to 10 0 in control register 1 (address 0x01); the result is stored in the y ? (z2) result register ( address 0x0 b) . the touch resistance (r touch ) can then be calculated using the following equation: r touch = (r xplate ) (x position /4096) [( z2 / z1 ) ? 1] (2) 07667-026 y? y+ x? x+ t ouch resist ance m easure z1 position x? x+ y? y+ t ouch resist ance measure x position y? y+ x? x+ t ouch resist ance measure z2 position figure 26 . three measurements required for touch pressure second method the second method requires the user to know the resistance of the x - plate and y - plate tablets. three touch screen conversions are required : a measurement of the x position (x position ), the y position (y position ), and the z1 positio n. the following equation also calculates the touch resistance (r touch ): r touch = r xplate (x position /4096) [(4096/ z1 ) ? 1] ? r yp late [1 ? ( y position /4096)] (3) temperature measurem ent a temperature measurement option called the single - conversion method is available on the ad7879/ad7889. the conversion method requires only a single measurement on adc cha nnel 001 . the r e sults are stored in the temperature conversion result register ( address 0x0d ). the ad7879 /ad7889 do not provide an explicit output of the temperature reading; the system must perform some external calculations. this method is based on an on - chip diode me a surement. the acquisition time is fixed at 16 ms for temperature me a surement. conversion method the conversion method makes use of the fact that the tempera - ture coefficient of a silicon diode is approximately ?2.1 mv/c. however, this small change is superimposed on the diode forward voltage, which can have a wide tolerance. therefore, it is necessary to calibrate by measuring the diode voltage at a known temperat ure to provide a baseline from which the change in forward voltage with temperature can be measured. this method provides a resolution of approximately 0.3c and a predicted accuracy of 2c. the temperature limit comparison is performed on the result in the temperature conversion result register ( address 0x0d ), which is the measurement of the diode forward voltage. the values programmed into the high and low limits should be referenced to the calibrated diode fo r ward voltage to make accurate limit compar isons.
ad7879/ad7889 rev. c | page 16 of 40 temperature calculations if an explicit temperature reading in degrees celsius is required, calculate for the single - measurement method as follows: 1. calculate the scale factor of the adc in degrees per lsb. degrees per lsb = adc lsb size / ?2.1 mv = ( v cc /4096)/ ?2.1 mv 2. save the adc output, d cal , at the calibration temperature, t cal . 3. take the adc reading, d amb , at the temperature to be measured, t amb . 4. calculate the difference in degrees between t cal and t amb by ?t = (d amb ? d cal ) degrees per lsb 5. add ? t to t cal . example using v cc = 2.5 v as reference, degrees per lsb = (2.5/4096)/ ? 2.1 10 ? 3 = ? 0.291 the adc output is 983 decimal at 25c, equivalent to a diode forward voltage of 0.6 v. the adc output at t amb is 880. ? t = (880 ? 983) ? 0.291 = 30c t am b = 25 + 30 = 55 c
ad7 879/ad7889 rev. c | page 17 of 40 median and averaging filters as explained in the touch screen principles section, touch screens are composed of two resistive layers, normally placed over an lcd screen. b e cause these layers are in close prox imity to the lcd screen, noise can be coupled from the screen onto these resistive layers , causing errors in the touch screen positional measurements. the ad7879 /ad7889 contain a filtering block to process the data and discard the spurious noise before se nding the infor - mation to the host. the purpose of this block is not only the suppression of noise ; the on - chip filtering also greatly reduces the host processing loading. the processing function consists of two filters that are applied to the converted re sults: the median filter and the averaging filter. the median filter suppresses the isolated out -of - range noise and sets the number of measurements to be taken. these measurements are arranged in a temporary array, where the first value is the smallest me asurement and the last value is the largest measure - ment. bit 6 and bit 5 in control register 2 (med1, med0) set the window of the median filter and, therefore, the number of measurements taken. table 8 . median filter size m ed 1 med0 number of measurements 0 0 median filter disabled 0 1 4 1 0 8 1 1 16 the averaging filter size determines the number of values to average. bit 8 and bit 7 in control register 2 (a vg 1, a vg 0) set the average to 2, 4, 8, or 16 samples. only the final averaged result is written into the result register. table 9 . averaging f ilter size a vg 1 avg0 filter size 0 0 average of 2 middle samples 0 1 average of 4 middle samples 1 0 average of 8 middle samples 1 1 average of 16 samples when both filter values are 00 , only one measurement is tran s ferred to the register map. the number specified with th e m ed 1 and m ed 0 settings must be greater than or equal to the number specified with the a vg 1 and a vg 0 settings. if both setting s specify the same number, the median filter is switched off. table 10. median averaging filter s (mavf) s ettings se tting function m = a median filter is disabled ; output is the average of a converted results m > a output is the average of the middle a values from the array of m measurements m < a not possible because the median filter size is always larger than the averaging window size example i n this example , m ed 1, m ed 0 = 11 and a vg 1, a vg 0 = 10 ; the median filter has a window size of 16. this means that 16 measu rements are taken and arranged in descending order in a temporary array. the averaging window size in this example is 8. the output is the average of the middle eight values of the 16 measurement s taken with the median filter. a veraging fi lter median fi lter 12-bit sar adc 6 2 13 4 16 5 15 10 9 3 11 8 1 12 14 7 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 m = 16 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 a = 8 converted resul ts 16 measurements arranged a verage of middle 8 v alues 07667-027 figure 27 . median and averaging filter example it takes approximately 2 s to s ort the data in the rank filter (t sort in figure 34 ); t sort adds to the update rate of the ad7879.
ad7879/ad7889 rev. c | page 18 of 40 aux/ v bat/gpio pin the aux/vbat/gpio pin on the ad7879/ad7889 can be programmed as an auxiliary input to t he adc, as a battery monitoring input, or as a general - purpose digital input/output. to select the auxiliary measurement, set the adc channel address to 011 (bits[14:12] in control register 1, address 0x01). to select a battery measurement, set the adc cha nnel address to 010. to select the gpio function , set bit 13 in control register 2 (address 0x02) to 1. auxiliary input the ad7879/ad7889 have an auxiliary analog input, aux. when the auxiliary input function is selected, the signal on the aux pin (aux/vba t/gpio) is connected directly to the adc input. this channel has a full - scale input range from 0 v to v cc . the adc channel address for aux is 011 (bits[14:12] in control register 1, address 0x01), and the result is stored in the aux/vbat result r egister ( address 0x0c ). battery input the ad7879/ad7889 can monitor battery voltages from 0.5 v to 5 v when the bat measurement is selected. figure 28 shows a block diagram of a battery voltage monitored through the vbat pin. the voltage t o the v cc pin (v cc /ref) of the ad7879/ad7889 is maintained at the desired supply voltage via the dc - to - dc converte r, and the input to the converte r is monitored. this voltage on v bat is divided by 4 internally, so that a 5 v battery voltage is pr e sented to the adc as 1.25 v. to conserve power, the divider circuit is on only during the sampling of a voltage on v bat. note that the possible maximum input is 5 v. the adc channel address for vbat is 010 (bits[14:12] in control register 1, address 0x01) , and the result is stored in the aux/vbat result r egister (address 0x0c ). adc 0.125v to 1.25v sw vbat v cc 12k? 4k? dc-to-dc converter battery 0.5v to 5v 07667-028 figure 28 . block diagram of battery measurement circuit the maximum battery voltage that the ad7879/ad7889 can measure changes when a different reference voltage i s used. the max i mum voltage that is measurable is v cc 4 because this voltage gives a full - scale output from the adc. the battery voltage ca n be calculated using the follow ing formula: v bat (v) = [ ( register value ) v cc 4]/4095 limit comparison the aux measurement and the battery measurement can be compared with high and low limits stored on chip. an out - of - limit result generates an alarm output at the int pin ( penirq / int / dav ) when t he int function is enabled. the high limit for both channels is stored in the aux/vbat high limit r egister (address 0x04 ), and the low limit is stored in the aux/vbat low limit r egister (address 0x05). after a measurement from either aux or v bat is taken, it is compared with the high and low limits. the out - of - limit comparison sets a status bit in control register 3. s eparate status bits for the high limit and the low limit indicate which limit was exceeded. the interrupt sou rces can be masked by clearing the corresponding enable bit in control register 3. gpio the ad7879/ad7889 have one general - purpose logic input/ output pin, gpio (aux/vbat/gpio) . to enable gpio, set bit 13 in control register 2 to 1. if this bit i s set to 0 , the aux/ v bat function is active on the pin. if the gpio is not enabled , t he other gpio configuration bits have no effect. the gpio data bit is bit 12 in control register 2. direction (bit 11, control register 2, address 0x02) bit 11 sets the direction of the gpio pin (aux/vbat/gpio) . when gpio dir = 0, the pin is an output. setting or clearing the gpio data bit ( bit 12 in control register 2 ) o utputs a value on the gpio pin. when gpio dir = 1, the pin is an input. an input value on the gpio pin sets or cle ars the gpio data bit (bit 12 in control register 2). gpio data register bits are read - only when gpio dir = 1. polarity (bit 10, control register 2, address 0x02) when gpio pol = 0, the gpio pin is active low. when gpio pol = 1, the gpio pin is active high . how this bit affects the gpio o pera tion also depends on the gpio dir bit. if gpio pol = 1 and gpio dir = 1, a 1 at the input pin sets the corres ponding gpio data register bit to 1. a 0 at the input pin clears the corresponding gpio data bit to 0. if gpio pol = 1 and gpio dir = 0, a 1 in the gpio data register bit puts a 1 on the corresponding gpio output pin. a 0 in the gpio data register bit puts a 0 on the gpio output pin. if gpio pol = 0 and gpio dir = 1, a 1 at the input pin sets the corre sponding gpi o data bit to 0. a 0 at the input pin clears the corresponding gpio data bit to 1. if gpio pol = 0 and gpio dir = 0, a 1 in the gpio data register bit puts a 0 on the corresponding gpio output pin. a 0 in the gpio data register bit puts a 1 on the gpio out put pin.
ad7 879/ad7889 rev. c | page 19 of 40 gpio interrupt enable (bit 12, control register 3, address 0x03) the gpio pin can operate as an interrupt source to trigger the int out put. this is controlled by bit 12 in control register 3. if the gpio alert interrupt en able bit is set to 0, the gpio can trigger int . if this bit is set to 1 , the gpio cannot trigger int . int is asserted if the gpio data register bit is set when the gpio is configured as an input , provided that int is enabled. int is triggered only when the gpio is configured as an input, that is, when gpio dir = 1. int is clea red only when the gpio signal or the gpio en able bit changes.
ad7879/ad7889 rev. c | page 20 of 40 c onversion timing conversion timing or u pdate rate is the rate at which the ad7879 provides converted values from the adc so that the xy positions in the touch screen can be updated. in other words, the update rate is the timing requir ed to give valid measurements in the sequencer. figure 29 shows conversion timing for a conversion sequence. f c d t measure f c d t measure f c d t measure f c d f c d t measure t measure t measure x+ m m m m m m y+ z1 z2 vba t/aux temp 07667-046 figure 29 . conversion timing sequence fcd is required before each touch scree n measurement (x+, y+, z1 , and z2). this time is required to allow the screen inputs to settle before converting. if the sequence does not contain any screen channel (v bat , aux , or temp), only one fcd is added at start of the sequence. at the end of the sequence, there is always another fcd. t measure is the time required to perform one measurement in the conversion sequence. t measure = [ acq (2 s, 4 s, 8 s, 16 s) + t conv (7.5 s) + t sort (2 s) ] where: acq is the acquisition time which is programmable i n control registe r 1. for temperature measurements, acq is fixed at 16 s. t conv (t ypical adc conversion time ) is specified at 7.5 s. t sort is the time needed to sort the new sample within the median filter array. the t sort value is approximately 2 s. if a median filter is not used (med =0), the t sort value is 0. t measure _ min = 9.5 s (acq = 2 s, no median filter ) conversion time per channel depends on the number of samples to be converted. the n umber of samples is pro - grammed using the following m edian filter settings: t channel = t measure med t channel _ min =9.5 s (acq = 2 s, m ed = 0) t channel _ max = 376 s (acq = 16 s, m ed = 16) update r ate = [ fcd + (t measure med) ] n + fcd + tmr where: n = number of channels to be measured (1 to 6) . med = median filter setting (1, 4, 8, 16) . tmr = timer setting (0 s to 9.4 ms) . the t otal update rate depends on the median filter settings and the number of channels in the conversion sequence. the t imer setting (tmr) allows the user more flexibility to program the update rate. for ex ample , if acq = 4 us med = 8 n = 2 fcd = 1.024 ms tmr = 620 s t measure = 4 + 7.5 + 2 = 13.5 s t channel = (13.5 8) = 108 s then update rate = [1024 + 108] 2 + 1024 + 620 = 3.9 ms
ad7879/ad7889 rev. c | page 21 of 40 register map table 11 . reg ister table address 1 register name description default value type 0x00 unused unused 0x0000 r/ w 0x01 control register 1 p en interrupt enable, channel selection for manual conversion, adc mode, ac quisition time, and conversion timer 0x0000 r/ w 0x02 control register 2 adc power management, gpio control, pen interrupt mode , averaging, m e dian filter, software reset, and fcd 0x4040 r/ w 0x03 control register 3 status of high/low limit comparisons for temp and aux/vbat, and enable bits to allow them to become interrupts; channel selection for slave/master mode 0x0000 r/ w 0x04 aux/vbat high limit aux/vbat high limit for comparison 0x0000 r/ w 0x05 aux/vbat low limit aux/vb at low limit for comparison 0x0000 r/ w 0x06 temp high limit temp high limit for comparison 0x0000 r/ w 0x07 temp low limit temp low limit for comparison 0x0000 r/ w 0x08 x+ x+ measurement for y positio n 0x0000 r 0x09 y+ y+ measurement for x position 0x0000 r 0x0a x+ (z1) x+ measurement for touch - pressure calculation (z1) 0x0000 r 0x0b y ? (z2) y ? measurement for touch - pressure calculation (z2) 0x0000 r 0x0c aux/vbat aux/vbat voltage measurement 0x0000 r 0x0d temp t emp erature conversion m easurement 0x0000 r 0x0e revision and device id revision and device id 0x0379 (ad7879-1/ad7889-1) r 0x037a (ad7879/ad7889) r 1 do not write to addr esses outside the register map .
ad7879/ad7889 rev. c | page 22 of 40 detailed register de scriptions all addresses and default values are expressed in h exadecimal. table 12 . control register 1 address bit name data bit description default value 0x01 disable penirq 15 pen interrupt enable . 0x0000 0 = penirq is enabled . 1 = penirq is disabled and int is enabled . chnl add[2:0] [14:12] adc c hannel address for manual conversion ( adc m ode = 01). 111 = x+ input (y position) . 110 = y+ input (x position) . 101 = x+ (z1) input for touch - pressure calculation. 100 = y ? (z2) input (used fo r touch - pressure measurement) . 011 = aux inpu t. 1 010 = vbat inpu t. 1 001 = temperature measurement. 000 = n ot applicable . adc mode[1: 0] [11:10] adc mode . 00 = n o conve rsion . 01 = s ingle conversio n. 2 10 = c onversion sequence (slave mode ). 2 11 = c onversion sequence (master mode) . acq[1:0] [9:8] adc acquisition time . 00 = 4 clock periods (2 s) . 01 = 8 clock peri ods (4 s) . 10 = 16 clock periods (8 s) . 11 = 32 clock periods (16 s) . note that the acquisition time does not apply to t he temperature sensor channels; t he temperature channel has a constant settling time of 16 s. tmr[7:0] [7:0] conversion interval timer . starts at 550 s (00000001) and continues to 9.440 ms (11111111) in steps of 35 s (see table 18). note that , in slave mode, the conversion interval timer starts to count as soon as the co n version sequence is fini shed; i n master mode, it starts to count again only if the screen remains touched . if the screen is released, the timer stops counting and, on the next screen touch, a conversion star ts immediately. 1 if gpio is enabled in control register 2 (bit 13) , aux and vbat are both ignored. if aux and vbat are both selected in control register 3 and gpio is disabled, aux is ignored and vbat is measured. 2 note that these bits are cleared to 00 at the end of the conversion sequence if the conversion interval timer bits in control register 1 (address 0x 01) bits [ 7:0 ] = 0x00 at the end of the conversion sequence.
ad7879/ad7889 rev. c | page 23 of 40 table 13 . control register 2 address bit name data bit description default value 0x02 pm[1:0] [15:14] adc power management. 0x4040 00 = full shutdown ; the adc, oscillator, bias , and temperature sensor are a ll powered down. 01 = a nalog blocks to be powered down depend on the adc mode . if adc mode is master mode , the adc, oscillator, bias , and temperature sensor are p o wered down and must wake up when the user touches the screen . if adc mode is s lave mode, the adc and temperature sensor are powered down wh en not being used. they wake up automatically when required. the oscillator and bias are powered up because they are needed to measure time. this also applies to the single - conversion mode. 10 = adc, bias , and oscillator are powered up continuously, irrespective of adc mode. 11 = same a s 01 . gpio en 13 gpio enable . 0 = aux/vbat channel active . 1 = gpio enabled on aux /vbat / gpio pin. gpio dat 12 gpio data bit . gpio dir 11 gpio direction . 0 = o utput . 1 = i nput . gpio pol 10 gpio polarity . 0 = gpio pin is active low . 1 = gpio pin is active high . ser/dfr 9 selects normal (single - ended) or ratiometric (differential) conversion . 0 = r atiometric (differential) . 1 = n ormal (single - ended) . a vg [1:0] [8:7] adc averaging . 00 = 2 middle values averaged (one measurement when median filter is disabled ). 01 = 4 middle values averaged . 10 = 8 middle values average d. 11 = 16 values averaged . m ed [1:0] [6:5] median filter size . 00 = m edian filter disabled. 01 = 4 measurements . 10 = 8 measurements . 11 = 16 measurements . sw/rst 4 software reset; digital logic is reset when this bit is set . fcd[3:0] [3:0] adc first conversion dela y. 1 starts at 128 s (default) and continues to 4.096 ms in steps of 128 s (see table 22). 1 this delay occurs before conversion of the x and y coordinate channel s (including z1 and z 2) to allow for screen settling and before the first conversion to allow the adc to power up.
ad7879/ad7889 rev. c | page 24 of 40 table 14 . control register 3 address bit name data bit description default value 0x03 temp mask 15 temp mask bit . 0x0000 0 = t emp erature measurement is allowed to cause interrupt . 1 = t emp erature measurement is not allowed to cause interrupt . au x /vbat mask 14 aux/vbat mask bit . 0 = aux/vbat measur ement is allowed to cause interrupt . 1 = aux/vbat measurement is not allowed to cause interrupt . int mode 13 dav / int mode select. 0 = enable dav mode . 1 = enable int mode . note that this bit overrides any mask bits associated with individual channels. gpio alert 12 gpio interrupt enable . 0 = gpio can cause an alert on the int output. 1 = mask gpio from causing an alert on the int output . aux/vbat low 11 1 = aux/vbat below low limit . aux/vbat high 10 1 = aux/vbat above high limit . temp low 9 1 = temp below low limit . temp high 8 1 = temp above high limit . x+ 7 1 = include measurement of y position (x+ input) . y+ 6 1 = include measurement of x position (y+ input) . z1 5 1 = include z1 touch - pressure measurement (x+ input). z2 4 1 = include measurement of z2 touch - pressure measurement (y ? input) . aux 3 1 = include measurement of aux channe l. 1 vbat 2 1 = include measurement of battery monitor (vbat ). 1 temp 1 1 = include temperature measurement . not u sed 0 unused . 1 if gpio is enabled in control register 2 (bit 13) , aux and vbat are both ignored. if aux and vbat are both selected and gpio is disabled, a ux is ignored and vbat is measured . table 15. limit registers address register name data bit description default value 0x04 aux/vbat high limit [15:0] user - programmable aux/vbat high limit register 0x0000 0x05 aux/vbat low limit [15:0] user - programmable aux/vbat low limit register 0x0000 0x06 t emp high limit [15:0] user - programmable temp high limit register 0x0000 0x07 temp low limit [15:0] user - programmable temp low limit register 0x0000
ad7879/ad7889 rev. c | page 25 of 40 table 16 . measurement result registers (read only) address register name data b it s description default value 0x08 x+ [15:0] measur ed x+ input with y excitation (y position) 0x0000 0x09 y+ [15:0] measured y+ input with x excitation ( x position) 0x0000 0x0a x+ (z1) [15:0] measured x+ input with x ? and y+ excitation (touch - pressure c alculation z1) 0x0000 0x0b y? (z2) [15:0] measured y ? input with x? and y+ excitation (touch - pressure calculation z2) 0x0000 0x0c aux/vbat [15:0] aux/vbat voltage measurement 0x0000 0x0d temp [15:0] temperature conversion measurement 0x0000 table 17 . revision and device id register (read only) address data bit s description default value 0x0e [15:12] unused 0x0379 (ad7879 -1/ad7889-1) 0x037a (ad7879/ad7889) [11:8] revision and device id bits [7:0] device id
ad7879/ad7889 rev. c | page 26 of 40 control regis ters disable penirq chn l add2 chn l add1 chn l add0 adc mode1 adc mode0 acq1 acq0 tmr7 tmr6 tmr5 tmr4 tmr3 tmr2 tmr1 tmr0 07667-029 15 0 figure 30 . control register 1 control register 1 control register 1 (address 0x01) contains the adc channel address and the adc mode bits. it sets the acquisition time and the timer. it also contains a bit to disable the pen interrupt. control register 1 should always be the last register programmed prior to starting conversions. its power - on default value is 0x0000. to change any parameter after conversion has begun, the part must first be put into adc mode 00. make the cha nges , and then reprogram control register 1, ensuring that it is always the last regi s ter programmed before conversions begin. timer (control register 1, bits[7:0]) the tmr bits in control register 1 set the conversion interval timer, which enables the ad c to perform a conversion sequence at regular intervals from 550 s (00000001) up to 9.440 ms (11111111) in increments of 35 s (see table 18 ). the default value of these bits is 00000000, which enables the adc to perform one conv ersion only. in slave mode, the timer starts as soon as the conversion sequence is finished. in master mode, the timer starts at the end of a conver - sion sequence only if the screen remains touched. if the touch is released at any stage , the timer stops . t he next time th at th e screen is touched, a conversion sequence begins immediately. table 18 . timer selection tmr [7:0] conversion interval 00000000 convert one time only (default) 00000001 every 550 s 00000010 every 585 s 00000011 every 620 s 11111101 every 9.370 ms 11111110 every 9.405 ms 11111111 every 9.440 ms acquisition time (control register 1, bits[9:8]) the acq bits in control register 1 allow the selection of acqu i si - tion times for the adc of 2 s (default), 4 s, 8 s, or 16 s. the user can program the adc with an acquisition time suit a ble for the type of signal being sampled. for example, signals with large rc time constants can re quire longer acquisition times. table 19 . acquisition time selection acq1 acq0 acquisition time 0 0 4 clock periods (2 s) 0 1 8 clock periods (4 s) 1 0 16 clock periods (8 s) 1 1 32 clock periods (16 s) adc mode (control register 1, bits[11:10]) the mode bits select the operating mode of the adc. the ad7879/ad7889 have three operating modes. these modes are selected by wri t ing to the mode bits in control register 1. if the mode bits are set to 00, no conversion is performed. table 20 . mode selection adc mode1 adc mode0 function 0 0 do not convert (default) 0 1 single - channel conversion ; the device is in slave mode 1 0 sequence 0 ; the device is in slave mode 1 1 sequence 1 ; the device is in master mode if the mode bits are set to 01, a single conversion i s performed on the channel selected by writing to the channel bits of control register 1 (bits[14:12]). at the end of the conversion, if the tmr bits in control register 1 are set to 00000000, the mode bits revert to 00 and the adc returns to no convert mo de until a new conversion is initiated by the host. setting the tmr bits to a value other than 00000000 causes the conversion to be repeated. the ad7879/ad7889 can also be programmed to automatically convert a sequence of selected channels. the two modes f or this type of conversion are slave mode and master mode. for slave mode operation, the channels to be digitized are selected by setting the corresponding bits in control register 3. conversion is initiated by writing 10 to the mode bits of control register 1. the adc then digitizes t he selected channels and stores the results in the corresponding result registers. at the end of the conversion, if the tmr bits in control register 1 are set to 00000000, the mode bits revert to 00 and the adc returns to no c onvert mode until a new co n version is initiated by the host. setting the tmr bits to a value other than 00000000 causes the conversion sequence to be repeated. for master mode operation, the channels to be digitized are written to control register 3 . mast er mode is then selected by writing 11 to the mode bits in control register 1. in this mode, the wake - up on touch feature is active ; therefore, conversion does not begin immediately. the ad7879/ad7889 wait until the screen is touched before beginning the sequence of conver - sions. the adc then digitizes the selected channels , and the results are written to the result registers. before beginning another sequence of conversions , the ad7879/ad7889 wait for the screen to be touched again or for a timer event if the screen remains touched .
ad7879/ad7889 rev. c | page 27 of 40 adc channel (control register 1 , bits[14:12]) the adc channel address is selected by bits[14:12] of control register 1 (chnl add2 to chnl add0). a complete list of channel addresses is given in table 21 . for single - channel conversion, the channel address is selected by writing the appropriate code to the chnl add2 to chnl add0 bits in control register 1. for sequential channel conversion, the channels to be converted are selected by setting the bits cor responding to the channel number in control register 3 for slave and master mode sequencing. for both single - channel and sequential conversion, a normal conversion (single - ended) is selected by setti ng the ser/ dfr bit in control reg ister 2 ( bit 9 ) . ratiometric (differential) co n version is selected by clearing the ser/ dfr bit. penirq enable (control register 1, bit 15) the ad7879/ad7889 have a dual function output that performs as penirq or int depending on the pen interrupt enable bit (bit 15 of control register 1). when this bit is set to 0, the pin functions as a pen interrupt and goes low whenever the screen is touched. when the pen interrupt enable bit is set to 1, the pen interrupt request is disabled and the pin functions as an interrupt when a measurement exceeds a preprogrammed limit ( int ). table 21 . codes for selecting input channel and normal or ratiometric conversion channel ser/ dfr ch nl add[ 2:0 ] analog input x switches y switches ref+ ref ? 0 0 111 x+ (y position) off on y+ y? 1 0 110 y+ (x position) on off x+ x? 2 0 101 x+ (z1 touch pressure) x+ off, x ? on y+ on, y ? off y+ x? 3 0 100 y ? (z2 touch pressure) x+ off , x ? on y+ on, y ? off y+ x? 4 0 011 aux off off v cc gnd 5 0 010 vbat off off v cc gnd 6 0 001 temp off off v cc gnd 0 000 invalid address 7 1 111 x+ (y position) off on v cc gnd 8 1 110 y+ (x position) on off v cc gnd 9 1 101 x+ (z1 touch pressure) off off v cc gnd 12 1 100 y ? (z2 touch pressure) off off v cc gnd 13 1 011 au x o ff off v cc gnd 14 1 010 vbat off off v cc gnd 15 1 001 temp off off v cc gnd 1 000 invalid address
ad7879/ad7889 rev. c | page 28 of 40 pm1 pm0 gpio en gpio dat gpio dir gpio pol avg1 avg0 med1 med0 sw/ rst fcd3 fcd2 fcd1 fcd0 07667-030 0 15 ser/ dfr figure 31 . control register 2 control register 2 control register 2 (address 0x02) contains the adc power management bit s, the gpio settings, the ser/ dfr bit (to choose the single - ended or differential method of touch screen measurement), the averaging and median filter settings, a bit that allows resetting of the part, and the first conversion delay bits. its power - on default value is 0x4040. see the detailed register descriptions section for more info r mation about the control registers. for information about the averaging and median filter settings, see the median and averaging filters section. for information about the gpio settings, see the gpio section. first conversion delay ( control register 2, bits [ 3:0 ]) the first conversion delay (fcd) bits in control register 2 pro gr am a delay from 128 s (default) up to 4.096 ms before the first conversion to allow the adc time to power up. this delay also occurs before c onversion of the x and y coordi nate channels to allow extra time for screen settling, and after the last conversi on in a sequence to precharge penirq . table 22 . first conversion delay selection fcd[3:0] delay 0000 128 s 0001 256 s 0010 384 s 0011 512 s 0100 640 s 0101 768 s 0110 896 s 0111 1.024 ms 1000 1.152 ms 1001 1.280 ms 1010 1.536 ms 1011 1.792 ms 1100 2.048 ms 1101 2.560 ms 1110 3.584 ms 1111 4.096 ms power management ( control register 2, bits[15:14]) the power management (pm) bits in control register 2 allow the power management features of the adc to be programmed (see table 23) . if the pm bits are set to 00, the adc is in full shut down. this setting overrides any setting of the mode bits in control register 1. power management overrides the adc modes. table 23 . power management selection pm1 pm0 function 0 0 full shutdown; adc, oscillator, bias , and temp - erature sensor are turned off. the only way to exit this mode is to write to the part over the serial interface and change the pm bits. this setting overrides any other setting on the part, including the adc mode bits. 0 1 the analog blocks to be powered down depend on the adc mode setting. in master mode, the adc, bias , temperature sensor, and oscillator are powered down and must wake u p when the user touches the screen. in slave mode, the adc and temperature sensor are powered down when not being used. they wake up automatically when required. the oscillator and bias are p o wered up because they are needed to measure time . this setting a lso applies to the single - conversion mode. 1 0 the adc, bias , and oscillator are powered up continuously , irrespective of adc mode. 1 1 same a s 01 .
ad7879/ad7889 rev. c | page 29 of 40 temp mask aux/ vbat mask int mode gpio alert aux/ vbat low aux/ vbat high temp high x+ y+ z1 z2 aux vbat temp not used 07667-031 0 15 temp low figure 32 . control register 3 control register 3 control register 3 (addre ss 0x03) includes the interrupt regi s ter (bits[15:8]) and the sequencer bits (bits[7:0]). sequencer (control register 3, bits[7:0]) the sequencer bits control which channels are converted during a conversion sequence in both slave mode and master mode. to include a measurement in a sequence, the relevant bit must be set in the sequence . setting bit 7 includes a measurement on the x+ channel (y position). setting bit 6 includes a measur e- ment on the y+ channel (x position), and so on (see table 14). figure 32 illustrates the correspondence between the bits in control register 3 and the various measurements. bi t 0 is not used. sla ve mode conversion sequence timer = 00? st art timer w a it for timer single conversion master mode w ait for first t ouch conversion sequence screen t ouched? timer = 00? st art timer w ait for timer screen t ouched? idle adc mode? 10 yes yes yes no no yes no no 11 00 07667-032 01 figure 33 . conversion modes fcd req?d? w ait for acquisition acq set channe l convert d at a a verage d at a transfer d at a t o registers set alert and interrupt 1 median # means median fi l ter size. rank new dat a (w ait t sort ) median # of samples t aken? 1 no yes 07667-033 st art of conversion sequence fcd fcd ma v fi lter enabled ? ou t -of- limit? end of sequence ? yes yes yes no no no yes no figure 34 . conversion sequence
ad7879/ad7889 rev. c | page 30 of 40 interrupts the ad7879/ad7889 have a dual function interrupt output, int , as well as a pen - down interrupt , penirq . the int output can be configured as a data avail able interrupt ( dav ) , as an out - of - limit interrupt ( int ) , or as a gpio interrupt. dav data available interrupt the behavior of the int errupt output is controlled by b it 13 in control register 3. in defa ult mode (bit 13 = 0 ) , int operates as a data available interrupt ( dav ). when the ad7879 /ad7889 finish a conversion or a conversion sequence, the interrupt is assert ed to let the host know that new adc data is ava ilable in the result registers. while the adc is idle or is converting, dav is high. when the adc has finished converting and new data has been written to the result registers , dav goes low. reading the result registers resets dav to a high condition. dav is also reset if a new con - version is started by the ad7879 /ad7889 because the timer expired. the host should read the result registers only when dav is low. to ensure correct operation of the dav mode when using the spi interface , it is necessary to write 0x00 00 to register 0x81 aft er a set of register reads. this clears the internal data read signal. adc converting setup by host idle new d at a av ailable host reads resul ts idle t conv ad7879/ ad7889 sta tus dav 07667-034 figure 35 . operation of dav output when the on - board timer is programmed to perform automatic conversions, limited time is available to the host to read the result registers before another sequence of conversions begins. the dav signal is reset high when the timer expires, and the host should not access the result registers while dav is high. int out - of - limit interrupt the int pin operates as an alarm or interrupt output when bit 13 in control r eg ister 3 (address 0x03 ) is set to 1. the output goes low if any one of the interrupt sources is asserted. the results of high and low limit comparisons on the aux, v bat , and temp channels are interrupt sources. an out - of - limit comparison sets a status bit i n the interrupt register. a separate status bit for the high limit and the low limit on each channel indicate s which limit was exceeded. the interrupt sources can be masked by setting the corresponding enable bit in this register to 1. there is one enable bit per channel. penirq pen interrupt the pen interrupt request output ( penirq ) goes low whenever the screen is touched and the penirq enable bit is set to 0 ( control register 1 , bit 15) . when penirq enable is set to 1, the pen interrupt request output is disabled. the pen interrupt equivalent output circuitry is shown in figure 36 . this digital logic output has an internal 50 k ? pull - up re sistor, so it does not need an external pull - up. the penirq out put idles high, and t he penirq circuitry is always enabled in m aster mode (adc mode = 11), except during conversions. 07667-035 x+ t o uch screen y+ 50k? y? x? penirq enable penirq v cc v cc figure 36 . penirq output equivalent circuit when the screen is touched, penirq goes low. this generates an interrupt request to the host. when the screen touch ends, penirq immediately goes high if the adc is idle . if the adc is converting, penirq goes high when the adc becomes idle. the penirq operation for these two conditions is shown in figure 37 . 07667-036 screen penirq adc sta tus t ouched not t ouched not t ouched not t ouched not t ouched adc idle screen penirq adc sta tus t ouched adc idle adc converting adc idle release not detected penirq detects release penirq detects release penirq detects t ouch penirq detects t ouch figure 37 . penirq operation for adc idle and adc converting
ad7879/ad7889 rev. c | page 31 of 40 synchronizing the ad 7879/ad7889 to the host cpu the two methods for synchronizing the ad7879 /ad7889 to its host cpu are slave mode (in which the mode bits are set to 01 or 1 0 ) and master mode (in which the mode bits set to 11 ). in master mode (adc mode bits = 1 1), penirq can be used as an interrupt to the host. when penirq goes low to indicate that the screen has been tou ched, the host is awakened. the host can then program the ad7879 /ad7889 to convert in any mode and read the results after the conversions are completed. in master mode, int or dav can also be used as an interrupt to the host. the host should first define a conversion sequence in control register 3, initialize the ad7879 /ad7889 in mode 1 1, and enable int or dav using bit 15 in control register 1 and bit 13 in control register 3. the hos t can then enter sleep mode to conserve power. the wake - up on touch feature of the ad7879/ad7889 is active in this mode; therefore, when the screen is touched, the programmed sequence of conversions automatically begins. when the int or dav signal is assert ed , the host reads the new data available in the ad7879 /ad7889 result registers and returns to sleep mode. this method can significantly reduce the load on the host. figure 38 shows how the penirq circuit is enabled. the wake - up on touch circuit and the penirq circuit are enabled only in master mode (adc mode = 11). in slave mode, the penirq / int / dav pin can output only int or dav signals. adc mode = 1 1? master mode 0 1 0 1 dav (end of conversion sequence) int (gpio alert/out of limits) int/d a v/gpio alert t ouch screen t ouched contro l register 3 bit 13 contro l register 1 bit 15 penirq/int/d a v pin t o the digi tal core enable w ake-u p on t ouch enable penirq detection circuit t ouch screen t ouched yes yes 07667-037 figure 38 . master mode operation
ad7879/ad7889 rev. c | page 32 of 40 serial interface the ad7879 and ad7879 - 1 (and the ad7889 and ad7889 - 1) differ only in the serial interface provided on the part. the ad7879 and the ad7889 are available with a serial peripheral interface (spi) . the ad7879 -1 and the ad7889 - 1 are available with an i 2 c- compatible interface. it is recommended that addresses outside the register map not b e written to . spi interface the ad7879/ad7889 have a 4 - wi re spi. the spi has a data input pin (din) for inputting data to the device, a data output pin (dout) for reading data back from the device, and a data clock pin (scl) for clocking data into and out of the device. a chip select pin ( cs ) enables or disables the serial interface. cs is required for correct operation of the spi interface. data is clocked out of the ad7879/ad7889 on the falling edge of scl , an d data is clocked into the device on the rising edge of scl. spi command word all data transactions on the spi bus begin with the master taking cs from high to low and sending out the command word. this indicates to the ad7879/ad7889 whether the t ransaction is a read or a write and gives the address of the register from which to begin the data transfer. the bit map in table 24 shows the spi command word. table 24 . spi command word msb lsb 15 14 13 12 11 10 [ 9:0 ] 1 1 1 0 0 r/ w register address bits[15:11] of the command word must be set to 11100 to successfully begin a bus transaction. bit 10 is the read/write bit; 1 indicates a read, and 0 indicates a w rite. bits[9:0] contain the target register address. when reading or writing to more than one register, this address indicates the address of the first register to be written to or read from. writing data data is written to the ad7879/ad7889 in 16 - bit word s. the first word written to the device is the command word, with the read/write bit set to 0. the master then supplies the 16 - bit input data - word on the din line. the ad7879/ad7889 clock the data into the register addressed in the command word. if there i s more than one word of data to be clocked in, the ad7879/ ad7889 automatically incre ment the address pointer and clock the next data - word into the following register. the ad7879/ad7889 continue to clock in data on the din line until the master ends the wr ite transition by pulling cs high or until the address pointer reaches its maximum value. the ad7879/ ad7889 address pointer does not wrap. when the address pointer reaches its maximum value, any data provided by the master on the di n line is ignored by the ad7879/ad7889. notes 1. data bits are latched on scl rising edges. scl can idle high or low between write operations. 2. all 32 bits must be written: 16 bits for the command word and 16 bits for data. 3. 16-bit command word settings for single write operation: cw[15:11] = 11100 (enable word) cw[10] = 0 (r/w) cw[9:0] = [ad9, ad8, ad7, ad6, ad5, ad4, ad3, ad2, ad1, ad0] (10-bit msb justified register address) cw 11 cw 10 cw 13 cw 12 din cw 15 cw 14 cw 9 cw 7 cw 6 cw 5 cw 4 cw 3 cw 2 cw 1 cw 0 d2 d1 d0 cw 8 t 4 t 8 16-bit command word 16-bit d at a 5 32 6 7 8 9 10 11 12 13 14 15 16 30 31 scl 1 2 3 4 d15 d14 d13 17 18 19 cs enable word r/w register address 07667-038 t 2 t 1 t 3 t 5 figure 39 . single register write , spi timing
ad7879/ad7889 rev. c | page 33 of 40 din cw 15 cw 14 cw 13 cw 8 cw 1 cw 0 d15 d14 scl cw 12 notes 1. multiple sequential registers can be loaded continuously. 2. the first (lowest address) register address is written, followed by multiple 16-bit data-words. 3. the address automatically increments with each 16-bit data-word (all 16 bits must be written). 4. cs is held low until the last desired register has been loaded. 5. 16-bit command word settings for sequential write operation: cw[15:11] = 11100 (enable word) cw[10] = 0 (r/w) cw[9:0] = [ad9, ad8, ad7, ad6, ad5, ad4, ad3, ad2, ad1, ad0] (starting msb justified register address) d1 d0 d1 d0 d15 dat a for s t arting register address dat a for next register address d15 d14 1 32 2 3 4 15 16 17 18 31 3433 4847 49 cs cw 11 cw 10 cw 9 cw 7 cw 2 cw 6 cw 5 cw 4 cw 3 11 12 13 14 5 6 7 8 9 10 16-bit command word enable word r/w st arting register address 07667-039 figure 40 . sequential register write , spi timing notes 1. data bits are latched on scl rising edges. scl can idle high or low between write operations. 2. the 16-bit command word must be written on din: 5 bits for enable word, 1 bit for r/w, and 10 bits for register address. 3. the register data is read back on the dout pin. 4. x denotes don?t care. 5. xxx denotes high impedance three-state output. 6. cs is held low until all register bits have been read back. 7. 16-bit command word settings for single readback operation: cw[15:11] = 11100 (enable word) cw[10] = 1 (r/w) cw[9:0] = [ad9, ad8, ad7, ad6, ad5, ad4, ad3, ad2, ad1, ad0] (10-bit msb justified register address) cw 11 cw 10 cw 13 cw 12 din cw 15 cw 14 cw 9 cw 7 cw 6 cw 5 cw 4 cw 3 cw 2 cw 1 cw 0 x x x cw 8 16-bit readback d at a 5 32 6 7 8 9 10 11 12 13 14 15 16 30 31 scl 1 2 3 4 x x x 17 18 19 cs xxx xxx xxx xxx dout xxx xxx xxx xxx xxx xxx xxx xxx xxx xxx xxx d2 d1 d0 xxx d15 d14 d13 xxx 16-bit command word enable word r/w register address t 4 t 5 t 1 t 3 t 2 t 6 t 7 t 8 07667-040 figure 41 . single register readb ack , spi timing reading data a read transaction begins when the master writes the command word to the ad7879/ad7889 with the read/write bit set to 1. the master then supplies 16 clock pulses per data - word t o be read, and the ad7879/ad7889 clock out data from the addressed register on the dout line. the first data - word is clocked out on the first falling edge of scl following the command word, as shown in figure 41. the ad7879/ad7889 continue to clock out data on the dout line provid ed that the master continues to supply the clock signal on scl. the read transaction ends when the master takes cs high. if the ad7879/ad7889 address pointer reaches its maximum val ue, the ad7879/ad7889 repeatedly clock out data from the addressed register. the address pointer does not wrap.
ad7879/ad7889 rev. c | page 34 of 40 07667-041 din cw 15 cw 14 cw 13 cw 8 cw 1 cw 0 x x scl cw 12 x x x x x readback data for starting register address x x 1 32 2 3 4 15 16 17 18 31 3433 4847 49 cs cw 11 cw 10 cw 9 cw 7 cw 2 cw 6 cw 5 cw 4 cw 3 11 12 13 14 5 6 7 8 9 10 xxx xxx xxx xxx d15 d14 d1 d0 d1 d0 d15 d15 d14 xxx xxx xxx xxx xxx xxx xxx xxx xxx xxx xxx xxx dout 16-bit command word enable word r/w starting register address notes 1. multiple sequential registers can be read back continuously. 2. the 16-bit command word must be written on din: 5 bits for enable word, 1 bit for r/w, and 10 bits for register address. 3. the address automatically increments with each 16-bit data-word being read back on the dout pin. 4. cs is held low until all register bits have been read back. 5. x denotes don?t care. 6. xxx denotes high impedance three-state output. 7. 16-bit command word settings for sequential readback operation: cw[15:11] = 11100 (enable word) cw[10] = 1 (r/w) cw[9:0] = [ad9, ad8, ad7, ad6, ad5, ad4, ad3, ad2, ad1, ad0] (starting msb justified register address) readback data for next register address figure 42 . sequential register readback, spi timing i 2 c- compatible interface the ad7879 -1 /ad7889 -1 support the industry standard 2 - wire i 2 c serial interface protocol. the two wires associated with the i 2 c timing are the scl and sda inputs. sda is an i/o pin that allows both r egister write and register read back operations. the ad7879 - 1/ad7889 - 1 are always slave devices on the i 2 c serial interface bus. the devices ha ve a 7 - bit device address, address 0101 1xx. the lower two bits are set by tying the add0 and add1 pins high or low. the ad7879 -1 /ad7889 -1 respond when the master device sends its device address over the bus. the ad7879 - 1/ad7889 - 1 cannot initiate data transfe rs on the bus. table 25. i 2 c device addresses for the ad7879 -1/ ad78 89-1 add1 add0 i 2 c a ddress 0 0 0101 100 0 1 0101 101 1 0 0101 110 1 1 0101 111 data transfer data is transferred over the i 2 c serial interface in 8 - bit bytes. t he master initiates a data trans fer by establishing a start con dition, defined as a high - to - low transition on the serial data line, sda, while the serial clock line, scl, remains high. this indicates that an address/data stream follows. all slave periphera ls connected to the serial bus respond to the start condition and shift in the next eight bits, co n sisting of a 7- bit address (msb first) plus a r/ w bit that determines the direction of the data transfer. the peripheral whose address cor responds to the transmitted address responds by pulling the data line low during the ninth clock pulse. this is known as the acknowledge bit. all other devices on the bus then remain idle while the selected device waits for data to be read from or written to it. if the r/ w bit is a 0 , the master writes to the slave device. if the r/ w bit is a 1 , the ma s ter reads from the slave device. data is sent over the serial bus in a sequ ence of nine clock pulses ( eight bits of data followed by an acknowledge bit from the slave device ) . transitions on the data line must occur during the low period of the clock signal and remain stable during the high period because a low - to - high trans i tion when the clock is high can be interpreted a s a stop signal. the number of data bytes transmitted over the serial bus in a single read or write operation is limited only by what the master and slave devices can ha n dle. when all data bytes are read or written, a stop condition is established. a stop condition is defined by a low - to - high transition on sda while scl remain s high. if the ad7879 - 1/ ad7889 - 1 encounter a stop condition, they return to the idle condition.
ad7879/ad7889 rev. c | page 35 of 40 notes 1. a start condition at the beginning is defined as a high-to-low transition on sda while scl remains high. 2. a stop condition at the end is defined as a low-to-high transition on sda while scl remains high. 3. 7-bit device address [dev a6:dev a0] = [01011xx], where the xs are don't care bits. 4. register data [d15:d8] and register data [d7:d0] are always separated by a low ack bit. sda dev a6 dev a5 dev a4 r/w scl dev a3 1 2 3 4 17 dev a2 dev a1 dev a0 ack a7 a6 11 16 5 6 7 8 9 10 st art ad7879-1/ad7889-1 device address a1 a0 register address[a7:a0] d15 d14 d9 d8 26 18 19 20 25 2827 34 29 35 d1 d0 d7 d6 register data[d15:d8] register d at a[d7:d0] ack ack 36 37 ack stop dev a6 dev a5 dev a4 1 2 3 st art t 1 ad7879-1/ad7889-1 device address 07667-042 t 3 t 2 t 4 t 5 t 6 t 8 t 7 figure 43 . example of i 2 c timing for single register write operation writing data over the i 2 c bus the process of writing to the ad7879 - 1/ad7889 - 1 over the i 2 c bus is shown in figure 43 and figure 45 . the device address is sent over the bus followed by the r/ w bit set to 0. this is followed by one byte of data that contains the 8 - bit address of the internal data register to be written. the bit map in table 26 shows the register address byte. table 26. i 2 c register address byte msb lsb 7 6 5 4 3 2 1 0 register address bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 the third data byte contains the eight msbs of the data to be written to the internal register. the fourth data byte contain s the eight lsbs of data to be written to the internal register. the ad7879 -1/ ad78 89- 1 address pointer register automatically increments after each write. this allows the master to sequentially write to all registers on the ad7879 - 1/ad7889 - 1 in the same wr ite transaction. however, the address pointer register does not wrap after the last address. any data written to the ad7879 - 1/ad7889 - 1 after the address pointer has reached its maximum value is discarded. all registers on the ad7879 - 1/ad7889 - 1 have 16 bi ts . two consecutive 8 - bit data bytes are combined and written to the 16- bit registers. to avoid errors, all writes to the device must contain an even number of data bytes. to end the transaction, the master generates a stop condition o n sda , or it generat es a repeat start condition if the master is to maintain control of the bus. reading data o ver the i 2 c bus to read from the ad7879 - 1/ad7889 - 1, the address pointer register must first be set to the address of the required internal register. the master performs a write transaction and writes to the ad7879 - 1/ad7889 - 1 to set the address pointer. the master then outputs a repeat start condition to keep control of the bus or, if this is not possible, the master ends the write transaction with a stop condition. a read transaction is initiated, with the r/ w bit set to 1. the ad7879 - 1/ad7889 - 1 supply the upper eight bits of data from the addre ssed register in the first read back byte, followed by the lower eight bits in the next byte. this is shown i n figure 44 and figure 45 . because the address pointer automatically incr ement s after each read, the ad7879 - 1/ad7889 - 1 continue to output readback data until the master puts a no acknowledge and a stop condition on the bus. if the address po inter reaches its maximum value and the master continues to read from the part, the ad7879 - 1/ ad7889 - 1 repeatedly send data fr om the last register addressed.
ad7879/ad7889 rev. c | page 36 of 40 notes 1. a start condition at the beginning is defined as a high-to-low transition on sda while scl remains high. 2. a stop condition at the end is defined as a low-to-high transition on sda while scl remains high. 3. the master generates the ack at the end of the readback to signal that it does not want additional data. 4. 7-bit device address [dev a6:dev a0] = [01011xx], where the two lsb xs are don't care bits. 5. register data [d15:d8] and register data [d7:d0] are always separated by a low ack bit. 6. the r/w bit is set to 1 to indicate a readback operation. sda dev a6 dev a5 dev a4 r/w scl dev a3 1 2 3 4 17 18 dev a2 dev a1 dev a0 ack a7 a6 11 16 5 6 7 8 9 10 st art ad7879-1/ad7889-1 device address a1 a0 register address[a7:a0] ack 26 19 21 25 2827 35 29 36 d1 d0 d7 d6 register d at a[d7:d0] sr ack 37 p dev a6 dev a5 dev a4 1 2 3 t 2 ad7879-1/ad7889-1 device address ad7879-1/ad7889-1 device address dev a6 dev a5 dev a1 dev a0 07667-043 r/w 20 30 26 19 21 25 2827 35 29 36 d1 d0 d7 d6 register d at a[d7:d0] s ack 37 p ad7879-1/ad7889-1 device address dev a6 dev a5 dev a1 dev a0 r/w 20 30 p using repeated st art sep ar a te read and write transactions ack ack t 1 t 3 t 4 t 4 t 5 t 5 t 6 t 8 t 7 figure 44 . example of i 2 c ti ming for single register readback operation 7-bit device address 7-bit device address register addr [7:0] read data high byte [15:8] read data low byte [7:0] read data high byte [15:8] read data low byte [7:0] w s p s r p ack ack ack ack ack . . . ack read (write transaction sets up register address) 7-bit device address 7-bit device address register addr [7:0] read data high byte [15:8] read data low byte [7:0] read data high byte [15:8] read data low byte [7:0] w s r p ack ack ack sr ack ack . . . ack read (using repeated start) s 7-bit device address register addr [7:0] write data high byte [15:8] write data low byte [7:0] write data high byte [15:8] write data low byte [7:0] w p ack ack ack ack ack . . . write output from master output from ad7879-1/ad7889-1 s = start bit p = stop bit sr = repeated start bit r = read bit w = write bit ack = acknowledge bit ack = no acknowledge bit 07667-044 figure 45 . example of sequential i 2 c write and read b ack operation
ad7879/ad7889 rev. c | page 37 of 40 grounding and layout for detailed information on grounding and layout considerations for the ad7879 /ad7889 , refer to the an - 577 application note, layout and grounding recommendations for touch screen digitizers . lead frame chip scale packages the lands on the lead frame chip scale package (cp - 16- 10) are rectangular. the printed circuit board (pcb) pad for these lands s hould be 0.1 mm longer than the package land length and 0.05 mm wider than the package land width. center the land on the pad to maximize the solder joint size. the bottom of the lead frame chip scale package has a central thermal pad. the thermal pad on the pcb should be at least as large as this exposed pad. to avoid shorting, provide a clearance of at least 0.25 mm between the thermal pad and the inner edges of the land pattern on the pcb. thermal vias can be used on the pcb thermal pad to improve the t hermal performance of the package. if vias are used, incorporate them in to the thermal pad at a 1.2 mm pitch grid. the via diameter should be between 0.3 mm and 0.33 mm , and the via barrel should be plated with 1 oz. of copper to plug the via. connect the pcb thermal pad to gnd. wlcsp assembly considerati ons for detailed information on the wlcsp pcb assembly and reliability, see the an - 617 application note, microcsp? wafer level chip scale package . nc = no connect 1 y+ 2 nc 3 nc 4 x? 11 nc 12 10 nc 9 dout 5 6 7 8 15 16 14 13 07667-045 ad7879/ ad7889 penirq/int/d av y? din gnd scl v cc /ref x+ aux/ vba t/ gpio cs t ouch screen 0.1f 0.1f t o 10f (optional) volt age regul at or main ba tte ry int sclk miso mosi spi inter f ace host cs figure 46 . typical application circuit
ad7879/ad7889 rev. c | page 38 of 40 outline dimensions 120808- a a b c d 1 2 3 bot t om view (bal l side up) top view (bal l side down) 0.36 0.32 0.28 0.17 0.15 0.13 1.50 ref bal l 1 identifier sea ting plane 0.50 ref 0.37 0.35 0.33 0.28 0.24 0.20 0.10 max coplanarit y 1.67 1.61 1.55 2.07 2.01 1.95 0.65 0.59 0.53 figure 47 . 12 - ball wafer level chip scale package [wlcsp] (cb - 12- 1) dimensions shown in millimeters 010410-a a b c d 0.650 0.59 5 0.540 1.555 1.505 1 .455 2.055 2.005 1.955 1 2 3 bottom view (ball side up) top view (ball si de d own) 0.340 0.320 0.300 1.50 ref ball 1 i dentifier seating plane 1.00 r ef 0.50 ref 0.380 0.355 0.330 0 .040 max 0.020 min 0.270 0.240 0.210 0.10 max coplanarity figure 48 . 12 - ball , backside - coated wafer level chip scale package [w lcsp] (cb - 12 -5) dimensions shown in millimeters 16 5 13 8 9 12 1 4 1.95 bsc pin 1 indic at or top view 4.00 bsc sq 3.75 bsc sq coplanarit y 0.08 exposed p ad (bot t om view) compliant t o jedec s t andards mo-220-vggc 12 max 1.00 0.85 0.80 sea ting plane 0.35 0.30 0.25 0.80 max 0.65 ty p 0.05 max 0.02 nom 0.20 ref 0.65 bsc 0.60 max 0.60 max pin 1 indic at or 0.50 0.40 0.30 0.25 min 2.50 2.35 sq 2.20 082008- a for proper connection of the exposed pad, refer to the pin configuration and function descriptions section of this data sheet. figure 49 . 16 - lead lead frame chip scale package [lfcsp_vq] 4 mm 4 mm , very thin quad (cp - 16 - 10) dimensions shown in millimeters
ad7879/ad7889 rev. c | page 39 of 40 ordering guide model 1 temperature range serial interface description package description package option branding ad7879acbz- rl ? 40c to +85c spi interface 12- ball wlcsp cb-12-1 t2y ad7879acbz-500r7 ? 40c to +85c spi interface 12- ball wlcsp cb-12-1 t2y ad7879acpz- rl ? 40c to +85c spi interface 16- lead lfcsp_vq cp-16-10 ad7879acpz-500r7 ? 40c to +85c spi interface 16- lead lfcsp_vq cp-16-10 ad7879-1acbz- rl ?40c to +85c i 2 c interface 12- ball wlcsp cb-12-1 t0q ad7879-1acbz-500r7 ?40c to +85c i 2 c interface 12- ball wlcsp cb-12-1 t0q ad7879- 1ac pz - rl ?40c to +85c i 2 c interface 16- lead lfcsp_vq cp-16-10 ad7879-1acpz-500r7 ?40c to +85c i 2 c interface 16- lead lfcsp_vq cp-16-10 ad7889 acbz -rl ?40c to +85c spi interface 12- ball, backside - coated wlcsp cb-12-5 t3r ad7889 acbz -500r7 ?40c to +85 c spi interface 12- ball, backside - coated wlcsp cb-12-5 t3r ad7889-1acbz- rl ?40c to +85c i 2 c interface 12- ball, backside - coated wlcsp cb-12-5 t3q ad7889-1acbz- rl 7 ?40c to +85c i 2 c interface 12- ball, backside - coated wlcsp cb-12-5 t3q ad7889-1acbz-500r7 ?40c to +85c i 2 c interface 12- ball, backside - coated wlcsp cb-12-5 t3q eval -ad7879ebz spi interface evaluation board eval -ad7879- 1ebz i 2 c interface evaluation board 1 z = rohs compliant part.
ad7879/ad7889 rev. c | page 40 of 40 notes i 2 c refers to a communications pro tocol originally developed by philips semiconductors (now nxp semiconductors) . ? 2008 C 2010 analog devices, inc. all rights reserved. trademarks and registered trademarks are the property of their respective owners. d07667 -0- 11 / 10(c)

▲Up To Search▲

Price & Availability of AD7889ACBZ-500R7

	To Download AD7889ACBZ-500R7 Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .